SMT-COMP

The International Satisfiability Modulo Theories (SMT) Competition.

GitHub

Home
Introduction
Benchmark Submission
Publications
SMT-LIB
Previous Editions

SMT-COMP 2023

Rules
Benchmarks
Specs
Model Validation Track
Proof Exhibition Track
Parallel & Cloud Tracks
Participants
Results
Statistics
Comparisons
Slides

Arith (Proof Exhibition Track)

Competition results for the Arith division in the Proof Exhibition Track.

Page generated on 2023-07-06 16:06:18 +0000

Benchmarks: 1700
Time Limit: 1200 seconds
Memory Limit: 60 GB

Logics: This track is experimental. Solvers are only ranked by performance, but no winner is selected.

Sequential Performance

Solver Error Score Correct Score CPU Time Score Wall Time ScoreUnsolvedAbstainedTimeout Memout
cvc5-lfsc 0 1582 9514.494 9510.471180116 0
cvc5 0 1573 9948.649 9919.2771270124 0
SMTInterpol 0 267 2000.917 927.697308112513 0

Parallel Performance

Solver Error Score Correct ScoreCPU Time ScoreWall Time ScoreUnsolvedAbstainedTimeout Memout
cvc5-lfsc 0 15829514.4949510.471180116 0
cvc5 0 15739948.6499919.2771270124 0
SMTInterpol 0 2672000.917927.697308112513 0

n Non-competing.
Abstained: Total of benchmarks in logics in this division that solver chose to abstain from. For SAT/UNSAT scores, this column also includes benchmarks not known to be SAT/UNSAT.