The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the Arith division in the Proof Exhibition Track.
Page generated on 2023-07-06 16:06:18 +0000
Benchmarks: 1700 Time Limit: 1200 seconds Memory Limit: 60 GB
Logics: This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Abstained | Timeout | Memout |
---|---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 1582 | 9514.494 | 9510.47 | 118 | 0 | 116 | 0 |
cvc5 | 0 | 1573 | 9948.649 | 9919.277 | 127 | 0 | 124 | 0 |
SMTInterpol | 0 | 267 | 2000.917 | 927.697 | 308 | 1125 | 13 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Abstained | Timeout | Memout |
---|---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 1582 | 9514.494 | 9510.47 | 118 | 0 | 116 | 0 |
cvc5 | 0 | 1573 | 9948.649 | 9919.277 | 127 | 0 | 124 | 0 |
SMTInterpol | 0 | 267 | 2000.917 | 927.697 | 308 | 1125 | 13 | 0 |
n Non-competing.
Abstained: Total of benchmarks in logics in this division that solver chose to abstain from. For SAT/UNSAT scores, this column also includes benchmarks not known to be SAT/UNSAT.