The International Satisfiability Modulo Theories (SMT) Competition.
Home
Introduction
Benchmark Submission
Publications
SMT-LIB
Previous Editions
Competition results for the LRA logic in the Proof Exhibition Track.
Page generated on 2023-07-06 16:06:18 +0000
Benchmarks: 425 Time Limit: 1200 seconds Memory Limit: 60 GB
This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 337 | 8909.325 | 8906.398 | 88 | 88 | 0 |
cvc5 | 0 | 335 | 8122.492 | 8108.996 | 90 | 90 | 0 |
SMTInterpol | 0 | 166 | 1776.149 | 804.844 | 259 | 3 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 337 | 8909.325 | 8906.398 | 88 | 88 | 0 |
cvc5 | 0 | 335 | 8122.492 | 8108.996 | 90 | 90 | 0 |
SMTInterpol | 0 | 166 | 1776.149 | 804.844 | 259 | 3 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.