The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the QF_UFIDL logic in the Proof Exhibition Track.
Page generated on 2022-08-10 11:19:33 +0000
Benchmarks: 300 Time Limit: 1200 seconds Memory Limit: 60 GB
This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
smtinterpol | 0 | 213 | 117228.39 | 112197.734 | 87 | 88 | 0 |
cvc5-lfsc | 0 | 88 | 270262.994 | 270283.771 | 212 | 212 | 0 |
veriT | 0 | 37 | 127227.532 | 127094.465 | 263 | 90 | 6 |
cvc5 | 0 | 9 | 346816.754 | 346874.062 | 291 | 288 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
smtinterpol | 0 | 213 | 120549.06 | 111610.308 | 87 | 85 | 0 |
cvc5-lfsc | 0 | 88 | 270307.604 | 270274.811 | 212 | 212 | 0 |
veriT | 0 | 37 | 127255.662 | 127083.555 | 263 | 89 | 6 |
cvc5 | 0 | 9 | 346878.264 | 346858.832 | 291 | 288 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.