The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the QF_UFDTLIRA logic in the Proof Exhibition Track.
Page generated on 2022-08-10 11:19:33 +0000
Benchmarks: 66 Time Limit: 1200 seconds Memory Limit: 60 GB
This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5 | 0 | 66 | 3.452 | 3.388 | 0 | 0 | 0 |
cvc5-lfsc | 0 | 66 | 4.133 | 4.077 | 0 | 0 | 0 |
smtinterpol | 0 | 66 | 50.605 | 26.974 | 0 | 0 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5 | 0 | 66 | 3.452 | 3.388 | 0 | 0 | 0 |
cvc5-lfsc | 0 | 66 | 4.133 | 4.077 | 0 | 0 | 0 |
smtinterpol | 0 | 66 | 50.605 | 26.974 | 0 | 0 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.