The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the QF_RDL logic in the Proof Exhibition Track.
Page generated on 2022-08-10 11:19:33 +0000
Benchmarks: 113 Time Limit: 1200 seconds Memory Limit: 60 GB
This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
veriT | 0 | 109 | 13494.704 | 13391.849 | 4 | 5 | 0 |
smtinterpol | 0 | 79 | 47098.992 | 45210.349 | 34 | 34 | 0 |
cvc5-lfsc | 0 | 64 | 67253.959 | 67268.286 | 49 | 49 | 0 |
cvc5 | 0 | 8 | 124542.43 | 124555.341 | 105 | 103 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
veriT | 0 | 109 | 13497.424 | 13374.009 | 4 | 4 | 0 |
smtinterpol | 0 | 79 | 47098.992 | 45210.349 | 34 | 34 | 0 |
cvc5-lfsc | 0 | 64 | 67267.019 | 67266.306 | 49 | 49 | 0 |
cvc5 | 0 | 8 | 124567.01 | 124549.641 | 105 | 103 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.