The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the QF_IDL logic in the Proof Exhibition Track.
Page generated on 2022-08-10 11:19:33 +0000
Benchmarks: 458 Time Limit: 1200 seconds Memory Limit: 60 GB
This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
veriT | 0 | 351 | 138754.364 | 138601.172 | 107 | 107 | 0 |
smtinterpol | 0 | 291 | 234269.056 | 226210.539 | 167 | 170 | 0 |
cvc5-lfsc | 0 | 266 | 264689.261 | 264754.343 | 192 | 192 | 0 |
cvc5 | 0 | 45 | 488397.733 | 488410.394 | 413 | 403 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
veriT | 0 | 351 | 138780.864 | 138595.952 | 107 | 107 | 0 |
smtinterpol | 0 | 291 | 237567.306 | 225214.371 | 167 | 165 | 0 |
cvc5-lfsc | 0 | 266 | 264758.431 | 264745.013 | 192 | 192 | 0 |
cvc5 | 0 | 45 | 488505.623 | 488388.504 | 413 | 403 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.