The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the QF_Equality division in the Proof Exhibition Track.
Page generated on 2022-08-10 11:19:33 +0000
Benchmarks: 2459 Time Limit: 1200 seconds Memory Limit: 60 GB
Logics: This track is experimental. Solvers are only ranked by performance, but no winner is selected.
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|
| smtinterpol | 0 | 2384 | 130378.289 | 112060.515 | 75 | 0 | 77 | 0 |
| cvc5-lfsc | 0 | 2380 | 328493.058 | 328317.265 | 79 | 0 | 77 | 0 |
| OpenSMT | 0 | 2170 | 23006.43 | 22851.495 | 10 | 279 | 10 | 0 |
| veriT | 0 | 2133 | 64635.541 | 64309.113 | 47 | 279 | 38 | 5 |
| cvc5 | 0 | 236 | 2595591.093 | 2595418.445 | 2223 | 0 | 2114 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|
| smtinterpol | 0 | 2384 | 132687.489 | 111585.436 | 75 | 0 | 75 | 0 |
| cvc5-lfsc | 0 | 2380 | 328508.118 | 328315.095 | 79 | 0 | 77 | 0 |
| OpenSMT | 0 | 2170 | 23006.86 | 22851.265 | 10 | 279 | 10 | 0 |
| veriT | 0 | 2133 | 64642.661 | 64306.833 | 47 | 279 | 38 | 5 |
| cvc5 | 0 | 236 | 2595939.543 | 2595313.045 | 2223 | 0 | 2114 | 0 |
n Non-competing.
Abstained: Total of benchmarks in logics in this division that solver chose to abstain from. For SAT/UNSAT scores, this column also includes benchmarks not known to be SAT/UNSAT.