The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the LRA logic in the Proof Exhibition Track.
Page generated on 2022-08-10 11:19:33 +0000
Benchmarks: 802 Time Limit: 1200 seconds Memory Limit: 60 GB
This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 666 | 179108.365 | 179093.825 | 136 | 136 | 0 |
cvc5 | 0 | 664 | 179186.229 | 179218.377 | 138 | 138 | 0 |
smtinterpol | 0 | 298 | 17731.902 | 15837.596 | 504 | 12 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 666 | 179133.205 | 179086.275 | 136 | 136 | 0 |
cvc5 | 0 | 664 | 179209.649 | 179210.797 | 138 | 138 | 0 |
smtinterpol | 0 | 298 | 17731.902 | 15837.596 | 504 | 12 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.