SMT-COMP

The International Satisfiability Modulo Theories (SMT) Competition.

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SMT-COMP 2022

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Proof Exhibition Track
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LRA (Proof Exhibition Track)

Competition results for the LRA logic in the Proof Exhibition Track.

Page generated on 2022-08-10 11:19:33 +0000

Benchmarks: 802
Time Limit: 1200 seconds
Memory Limit: 60 GB

This track is experimental. Solvers are only ranked by performance, but no winner is selected.

Sequential Performance

Solver Error Score Correct Score CPU Time Score Wall Time ScoreUnsolvedTimeout Memout
cvc5-lfsc 0 666 179108.365 179093.825136136 0
cvc5 0 664 179186.229 179218.377138138 0
smtinterpol 0 298 17731.902 15837.59650412 0

Parallel Performance

Solver Error Score Correct ScoreCPU Time ScoreWall Time ScoreUnsolvedTimeout Memout
cvc5-lfsc 0 666179133.205179086.275136136 0
cvc5 0 664179209.649179210.797138138 0
smtinterpol 0 29817731.90215837.59650412 0

n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.