SMT-COMP

The International Satisfiability Modulo Theories (SMT) Competition.

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SMT-COMP 2022

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Proof Exhibition Track
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LIA (Proof Exhibition Track)

Competition results for the LIA logic in the Proof Exhibition Track.

Page generated on 2022-08-10 11:19:33 +0000

Benchmarks: 266
Time Limit: 1200 seconds
Memory Limit: 60 GB

This track is experimental. Solvers are only ranked by performance, but no winner is selected.

Sequential Performance

Solver Error Score Correct Score CPU Time Score Wall Time ScoreUnsolvedTimeout Memout
cvc5-lfsc 0 263 3643.537 3645.23733 0
cvc5 0 253 13141.991 13109.4651310 0
smtinterpol 0 179 26719.264 26311.6868718 0
veriT 0 169 36648.385 36648.0289727 2

Parallel Performance

Solver Error Score Correct ScoreCPU Time ScoreWall Time ScoreUnsolvedTimeout Memout
cvc5-lfsc 0 2633645.2473645.07733 0
cvc5 0 25313145.38113108.9851310 0
smtinterpol 0 17926719.26426311.6868718 0
veriT 0 16936649.02536647.4789727 2

n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.