The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the LIA logic in the Proof Exhibition Track.
Page generated on 2022-08-10 11:19:33 +0000
Benchmarks: 266 Time Limit: 1200 seconds Memory Limit: 60 GB
This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 263 | 3643.537 | 3645.237 | 3 | 3 | 0 |
cvc5 | 0 | 253 | 13141.991 | 13109.465 | 13 | 10 | 0 |
smtinterpol | 0 | 179 | 26719.264 | 26311.686 | 87 | 18 | 0 |
veriT | 0 | 169 | 36648.385 | 36648.028 | 97 | 27 | 2 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 263 | 3645.247 | 3645.077 | 3 | 3 | 0 |
cvc5 | 0 | 253 | 13145.381 | 13108.985 | 13 | 10 | 0 |
smtinterpol | 0 | 179 | 26719.264 | 26311.686 | 87 | 18 | 0 |
veriT | 0 | 169 | 36649.025 | 36647.478 | 97 | 27 | 2 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.