SMT-COMP

The International Satisfiability Modulo Theories (SMT) Competition.

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SMT-COMP 2022

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Proof Exhibition Track
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Bitvec (Proof Exhibition Track)

Competition results for the Bitvec division in the Proof Exhibition Track.

Page generated on 2022-08-10 11:19:33 +0000

Benchmarks: 2660
Time Limit: 1200 seconds
Memory Limit: 60 GB

Logics: This track is experimental. Solvers are only ranked by performance, but no winner is selected.

Sequential Performance

Solver Error Score Correct Score CPU Time Score Wall Time ScoreUnsolvedAbstainedTimeout Memout
cvc5-lfsc 0 2389 335128.247 335156.5392710264 0
cvc5 0 2176 559695.409 559528.0774840449 0

Parallel Performance

Solver Error Score Correct ScoreCPU Time ScoreWall Time ScoreUnsolvedAbstainedTimeout Memout
cvc5-lfsc 0 2389335173.347335146.7592710264 0
cvc5 0 2176559780.099559505.8174840449 0

n Non-competing.
Abstained: Total of benchmarks in logics in this division that solver chose to abstain from. For SAT/UNSAT scores, this column also includes benchmarks not known to be SAT/UNSAT.