The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the Bitvec division in the Proof Exhibition Track.
Page generated on 2022-08-10 11:19:33 +0000
Benchmarks: 2660 Time Limit: 1200 seconds Memory Limit: 60 GB
Logics:
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Abstained | Timeout | Memout |
---|---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 2389 | 335128.247 | 335156.539 | 271 | 0 | 264 | 0 |
cvc5 | 0 | 2176 | 559695.409 | 559528.077 | 484 | 0 | 449 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Abstained | Timeout | Memout |
---|---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 2389 | 335173.347 | 335146.759 | 271 | 0 | 264 | 0 |
cvc5 | 0 | 2176 | 559780.099 | 559505.817 | 484 | 0 | 449 | 0 |
n Non-competing.
Abstained: Total of benchmarks in logics in this division that solver chose to abstain from. For SAT/UNSAT scores, this column also includes benchmarks not known to be SAT/UNSAT.