The International Satisfiability Modulo Theories (SMT) Competition.
Home
Introduction
Benchmark Submission
Publications
SMT-LIB
Previous Editions
Competition results for the AUFBVDTLIA logic in the Unsat Core Track.
Page generated on 2022-08-10 11:18:51 +0000
Benchmarks: 166 Time Limit: 1200 seconds Memory Limit: 60 GB
Sequential Performance | Parallel Performance |
---|---|
cvc5 | cvc5 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
2021-cvc5-ucn | 0 | 60 | 64171.046 | 64182.287 | 53 | 0 |
cvc5 | 0 | 60 | 67395.452 | 67405.557 | 55 | 1 |
z3-4.8.17n | 0 | 55 | 65850.117 | 65862.989 | 54 | 0 |
UltimateEliminator+MathSAT | 0 | 0 | 767.573 | 456.022 | 0 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
2021-cvc5-ucn | 0 | 60 | 64180.556 | 64180.577 | 53 | 0 |
cvc5 | 0 | 60 | 67403.042 | 67403.077 | 55 | 1 |
z3-4.8.17n | 0 | 55 | 65859.577 | 65859.569 | 54 | 0 |
UltimateEliminator+MathSAT | 0 | 0 | 767.573 | 456.022 | 0 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.