The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the UFLRA logic in the Incremental Track.
Page generated on 2021-07-18 17:30:28 +0000
Benchmarks: 935 Time Limit: 1200 seconds Memory Limit: 60 GB
Parallel Performance |
---|
cvc5-inc |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
2019-Z3n | 0 | 358440 | 151094.059 | 150877.017 | 235425 | 57 | 0 |
z3n | 0 | 356876 | 154388.925 | 154176.291 | 236989 | 63 | 0 |
2020-z3n | 0 | 355793 | 154659.883 | 154522.758 | 238072 | 64 | 0 |
cvc5-inc | 0 | 136983 | 44601.384 | 44452.795 | 456882 | 20 | 0 |
SMTInterpol | 0 | 129185 | 377778.349 | 371224.596 | 464680 | 224 | 0 |
UltimateEliminator+MathSAT | 0 | 0 | 3876.206 | 1724.72 | 593865 | 0 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.