The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the UFIDL logic in the Unsat Core Track.
Page generated on 2021-07-18 17:31:25 +0000
Benchmarks: 30 Time Limit: 1200 seconds Memory Limit: 60 GB
Sequential Performance | Parallel Performance |
---|---|
cvc5-uc | cvc5-uc |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
2020-z3n | 0 | 1916 | 1.437 | 1.461 | 0 | 0 |
cvc5-uc | 0 | 1916 | 1.94 | 1.926 | 0 | 0 |
z3n | 0 | 1915 | 1.058 | 1.068 | 0 | 0 |
2020-CVC4-ucn | 0 | 1915 | 2.313 | 2.361 | 0 | 0 |
Vampire | 0 | 999 | 2402.347 | 2402.351 | 2 | 0 |
SMTInterpol-remus | 0 | 983 | 4549.37 | 4405.948 | 3 | 0 |
SMTInterpol | 0 | 982 | 3646.238 | 3624.997 | 3 | 0 |
UltimateEliminator+MathSAT | 0 | 0 | 154.645 | 88.788 | 0 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
2020-z3n | 0 | 1916 | 1.437 | 1.461 | 0 | 0 |
cvc5-uc | 0 | 1916 | 1.94 | 1.926 | 0 | 0 |
z3n | 0 | 1915 | 1.058 | 1.068 | 0 | 0 |
2020-CVC4-ucn | 0 | 1915 | 2.313 | 2.361 | 0 | 0 |
Vampire | 0 | 999 | 2402.347 | 2402.351 | 2 | 0 |
SMTInterpol-remus | 0 | 983 | 4549.37 | 4405.948 | 3 | 0 |
SMTInterpol | 0 | 982 | 3646.238 | 3624.997 | 3 | 0 |
UltimateEliminator+MathSAT | 0 | 0 | 154.645 | 88.788 | 0 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.