The International Satisfiability Modulo Theories (SMT) Competition.
Home
Introduction
Benchmark Submission
Publications
SMT-LIB
Previous Editions
Competition results for the UF logic in the Incremental Track.
Page generated on 2021-07-18 17:30:28 +0000
Benchmarks: 2033 Time Limit: 1200 seconds Memory Limit: 60 GB
| Parallel Performance |
|---|
| cvc5-inc |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
|---|---|---|---|---|---|---|---|
| 2020-z3n | 0 | 97772 | 1187227.564 | 1187144.895 | 260326 | 920 | 1 |
| z3n | 0 | 97315 | 1195413.48 | 1195294.115 | 260783 | 919 | 4 |
| cvc5-inc | 0 | 23524 | 999859.822 | 999780.802 | 334574 | 823 | 0 |
| SMTInterpol | 0 | 15426 | 2110948.198 | 2088016.641 | 342672 | 1662 | 0 |
| UltimateEliminator+MathSAT | 0 | 0 | 8917.9 | 3931.144 | 358098 | 0 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.