The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the LRA logic in the Incremental Track.
Page generated on 2021-07-18 17:30:28 +0000
Benchmarks: 5 Time Limit: 1200 seconds Memory Limit: 60 GB
Parallel Performance |
---|
cvc5-inc |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-inc | 0 | 15969 | 73.531 | 72.759 | 0 | 0 | 0 |
2020-CVC4-incn | 0 | 15969 | 127.696 | 126.892 | 0 | 0 | 0 |
UltimateEliminator+MathSAT | 0 | 15969 | 463.521 | 330.641 | 0 | 0 | 0 |
2020-z3n | 0 | 13585 | 3612.148 | 3611.857 | 2384 | 3 | 0 |
z3n | 0 | 13584 | 3614.615 | 3614.301 | 2385 | 3 | 0 |
SMTInterpol | 0 | 12719 | 1232.181 | 1211.6 | 3250 | 1 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.