The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the LIA logic in the Unsat Core Track.
Page generated on 2021-07-18 17:31:25 +0000
Benchmarks: 227 Time Limit: 1200 seconds Memory Limit: 60 GB
| Sequential Performance | Parallel Performance |
|---|---|
| cvc5-uc | cvc5-uc |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
|---|---|---|---|---|---|---|
| 2020-CVC4-ucn | 0 | 9 | 11.171 | 11.226 | 0 | 0 |
| z3n | 0 | 9 | 1672.18 | 1672.906 | 1 | 0 |
| cvc5-uc | 0 | 8 | 1212.524 | 1212.782 | 1 | 0 |
| Vampire | 0 | 1 | 12313.101 | 12376.091 | 10 | 0 |
| SMTInterpol-remus | 0 | 0 | 23522.649 | 23177.762 | 15 | 0 |
| SMTInterpol | 0 | 0 | 23525.891 | 23181.932 | 15 | 0 |
| UltimateEliminator+MathSAT | 1 | 4 | 16821.321 | 15732.059 | 11 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
|---|---|---|---|---|---|---|
| 2020-CVC4-ucn | 0 | 9 | 11.171 | 11.226 | 0 | 0 |
| z3n | 0 | 9 | 1672.22 | 1672.856 | 1 | 0 |
| cvc5-uc | 0 | 8 | 1212.764 | 1212.762 | 1 | 0 |
| Vampire | 0 | 1 | 13034.411 | 12376.041 | 10 | 0 |
| SMTInterpol-remus | 0 | 0 | 23522.649 | 23177.762 | 15 | 0 |
| SMTInterpol | 0 | 0 | 23525.891 | 23181.932 | 15 | 0 |
| UltimateEliminator+MathSAT | 1 | 4 | 16821.321 | 15732.059 | 11 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.