The International Satisfiability Modulo Theories (SMT) Competition.
Home
Introduction
Benchmark Submission
Publications
SMT-LIB
Previous Editions
Competition results for the LIA logic in the Incremental Track.
Page generated on 2021-07-18 17:30:28 +0000
Benchmarks: 6 Time Limit: 1200 seconds Memory Limit: 60 GB
| Parallel Performance |
|---|
| cvc5-inc |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
|---|---|---|---|---|---|---|---|
| 2020-z3n | 0 | 25393 | 8.669 | 6.599 | 0 | 0 | 0 |
| z3n | 0 | 25393 | 9.041 | 8.127 | 0 | 0 | 0 |
| cvc5-inc | 0 | 25393 | 26.198 | 21.37 | 0 | 0 | 0 |
| 2020-CVC4-incn | 0 | 25393 | 61.683 | 60.359 | 0 | 0 | 0 |
| UltimateEliminator+MathSAT | 0 | 25393 | 281.092 | 166.319 | 0 | 0 | 0 |
| SMTInterpol | 0 | 25391 | 82.765 | 29.914 | 2 | 0 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.