The International Satisfiability Modulo Theories (SMT) Competition.
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Page generated on 2020-07-04 11:48:00 +0000
| Parallel Performance |
|---|
| CVC4-inc |
| Solver | Correct Score | Time Score | Division |
|---|---|---|---|
| CVC4-inc | 0.06594954 | 4.036e-05 | UF |
| CVC4-inc | 0.00480092 | 0.0 | UFLRA |
| Yices2 incremental | 0.0045792 | 0.00581871 | QF_UFLIA |
| Yices2 incremental | 0.00209716 | 0.00380876 | QF_AUFLIA |
| Bitwuzla | 0.00091387 | 0.02909676 | QF_ABV |
| Yices2 incremental | 0.00078822 | 0.00217774 | QF_LIA |
| Yices2 incremental | 0.00063181 | 0.00163031 | QF_AUFBV |
| CVC4-inc | 0.00031575 | 0.00371626 | QF_BV |
| Bitwuzla | 0.00019816 | 0.07632875 | QF_UFBV |
| Yices2 incremental | 0.00017177 | 0.0 | QF_LRA |
| SMTInterpol | 8.919e-05 | 0.02097954 | QF_UFLRA |
| CVC4-inc | 8.001e-05 | 0.00054438 | LRA |
| Yices2 incremental | 0.0 | 0.03645146 | QF_UF |
| SMTInterpol | 0.0 | 0.0003328 | LIA |
n Non-competing.
e Experimental.