The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the UFLRA logic in the Incremental Track. Chart
Results were generated on 2025-08-11
Benchmarks: 935
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|
| cvc5 | - | - | SMTInterpol |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 141390 | 30228.53 | 30228.53 | 0 | 935 | 0 | 7 | 0 |
| SMTInterpol | 0 | 130269 | 260393.32 | 260393.32 | 0 | 935 | 0 | 169 | 0 |
| UltimateEliminator+MathSAT | 0 | 0 | 3344.04 | 1908.31 | 0 | 935 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| SMTInterpol | 0 | 121572 | 1089.27 | 1089.27 | 0 | 490 | 445 | 0 | 0 |
| cvc5 | 0 | 107278 | 3235.48 | 3235.48 | 0 | 786 | 149 | 0 | 0 |
| UltimateEliminator+MathSAT | 0 | 0 | 3344.04 | 1908.31 | 0 | 935 | 0 | 0 | 0 |