SMT-COMP 2025

The International Satisfiability Modulo Theories (SMT) Competition.

GitHub

SMT-COMP 2025

UFDTNIA (Unsat Core Track)

Competition results for the UFDTNIA logic in the Unsat Core Track. Chart

Results were generated on 2025-08-11

Benchmarks: 503
Time Limit: 1200 seconds
Memory Limit: 30720 GB

Winners

Sequential Performance Parallel Performance SAT Performance (parallel) UNSAT Performance (parallel) 24 seconds Performance (parallel)
cvc5 cvc5 - cvc5 cvc5

Sequential Performance Performance

Solver Error Score Correct Score CPU Time Score Wall Time Score Solved Solved UNSAT Unsolved Abstained Timeout Memout
cvc5 0 242553 22217.23 22248.17 220 220 283 0 260 0
SMTInterpol 0 81950 1448.94 606.10 54 54 449 0 195 0

Parallel Performance Performance

Solver Error Score Correct Score CPU Time Score Wall Time Score Solved Solved UNSAT Unsolved Abstained Timeout Memout
cvc5 0 242553 22217.23 22248.17 220 220 283 0 260 0
SMTInterpol 0 81950 1448.94 606.10 54 54 449 0 195 0

UNSAT Performance Performance

Solver Error Score Correct Score CPU Time Score Wall Time Score Solved Solved UNSAT Unsolved Abstained Timeout Memout
cvc5 0 242553 22217.23 22248.17 220 220 283 0 260 0
SMTInterpol 0 81950 1448.94 606.10 54 54 449 0 195 0

24 seconds Performance Performance

Solver Error Score Correct Score CPU Time Score Wall Time Score Solved Solved UNSAT Unsolved Abstained Timeout Memout
cvc5 0 122705 552.83 570.12 139 139 6 358 0 0
SMTInterpol 0 67222 699.14 294.37 47 47 0 456 0 0