The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the UFDTNIA logic in the Incremental Track. Chart
Results were generated on 2025-08-11
Benchmarks: 139
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|
| cvc5 | - | - | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 404 | 47391.24 | 47417.11 | 0 | 139 | 0 | 56 | 0 |
| SMTInterpol | 0 | 63 | 177013.99 | 145411.80 | 0 | 139 | 0 | 128 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 321 | 137.27 | 137.27 | 0 | 95 | 44 | 17 | 0 |
| SMTInterpol | 0 | 44 | 21.56 | 21.56 | 0 | 18 | 121 | 7 | 0 |