The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the UFDTLIRA logic in the Unsat Core Track. Chart
Results were generated on 2025-08-11
Benchmarks: 2861
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Sequential Performance | Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|---|
| cvc5 | cvc5 | - | cvc5 | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 75879 | 507.36 | 864.44 | 2860 | 2860 | 1 | 0 | 0 | 0 |
| SMTInterpol | 0 | 71095 | 12204.65 | 8896.96 | 2736 | 2736 | 125 | 0 | 90 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 75879 | 507.36 | 864.44 | 2860 | 2860 | 1 | 0 | 0 | 0 |
| SMTInterpol | 0 | 71095 | 12204.65 | 8896.96 | 2736 | 2736 | 125 | 0 | 90 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 75879 | 507.36 | 864.44 | 2860 | 2860 | 1 | 0 | 0 | 0 |
| SMTInterpol | 0 | 71095 | 12204.65 | 8896.96 | 2736 | 2736 | 125 | 0 | 90 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 75879 | 507.36 | 864.44 | 2860 | 2860 | 1 | 0 | 0 | 0 |
| SMTInterpol | 0 | 69801 | 4734.39 | 2445.25 | 2713 | 2713 | 10 | 138 | 0 | 0 |