The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the UFDTLIA logic in the Unsat Core Track. Chart
Results were generated on 2025-08-11
Benchmarks: 627
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Sequential Performance | Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|---|
| cvc5 | cvc5 | - | cvc5 | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 325995 | 21981.10 | 22048.76 | 525 | 525 | 102 | 0 | 71 | 0 |
| SMTInterpol | 0 | 68816 | 5761.07 | 4313.46 | 128 | 128 | 499 | 0 | 359 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 325995 | 21981.10 | 22048.76 | 525 | 525 | 102 | 0 | 71 | 0 |
| SMTInterpol | 0 | 69358 | 6980.91 | 5251.25 | 128 | 128 | 499 | 0 | 359 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 325995 | 21981.10 | 22048.76 | 525 | 525 | 102 | 0 | 71 | 0 |
| SMTInterpol | 0 | 69358 | 6980.91 | 5251.25 | 128 | 128 | 499 | 0 | 359 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 288046 | 1513.58 | 1574.97 | 495 | 495 | 16 | 116 | 0 | 0 |
| SMTInterpol | 0 | 66038 | 679.30 | 253.28 | 116 | 116 | 0 | 511 | 0 | 0 |