SMT-COMP 2025

The International Satisfiability Modulo Theories (SMT) Competition.

GitHub

SMT-COMP 2025

UFBVDTNIRA (Unsat Core Track)

Competition results for the UFBVDTNIRA logic in the Unsat Core Track. Chart

Results were generated on 2025-08-11

Benchmarks: 493
Time Limit: 1200 seconds
Memory Limit: 30720 GB

Winners

Sequential PerformanceParallel PerformanceSAT Performance (parallel)UNSAT Performance (parallel)24 seconds Performance (parallel)
cvc5cvc5-cvc5cvc5

Sequential Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved UNSATUnsolvedAbstainedTimeoutMemout
cvc5025595308.21368.314854858080
SMTInterpol02236110619.469125.19418418750690

Parallel Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved UNSATUnsolvedAbstainedTimeoutMemout
cvc5025595308.21368.314854858080
SMTInterpol02236110619.469125.19418418750690

UNSAT Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved UNSATUnsolvedAbstainedTimeoutMemout
cvc5025595308.21368.314854858080
SMTInterpol02236110619.469125.19418418750690

24 seconds Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved UNSATUnsolvedAbstainedTimeoutMemout
cvc502556394.33154.274844840900
SMTInterpol0213431410.21556.8940040009300