SMT-COMP 2025

The International Satisfiability Modulo Theories (SMT) Competition.

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SMT-COMP 2025

UFBVDTNIRA (Unsat Core Track)

Competition results for the UFBVDTNIRA logic in the Unsat Core Track. Chart

Results were generated on 2025-08-11

Benchmarks: 493
Time Limit: 1200 seconds
Memory Limit: 30720 GB

Winners

Sequential Performance Parallel Performance SAT Performance (parallel) UNSAT Performance (parallel) 24 seconds Performance (parallel)
cvc5 cvc5 - cvc5 cvc5

Sequential Performance Performance

Solver Error Score Correct Score CPU Time Score Wall Time Score Solved Solved UNSAT Unsolved Abstained Timeout Memout
cvc5 0 25595 308.21 368.31 485 485 8 0 8 0
SMTInterpol 0 22361 10619.46 9125.19 418 418 75 0 69 0

Parallel Performance Performance

Solver Error Score Correct Score CPU Time Score Wall Time Score Solved Solved UNSAT Unsolved Abstained Timeout Memout
cvc5 0 25595 308.21 368.31 485 485 8 0 8 0
SMTInterpol 0 22361 10619.46 9125.19 418 418 75 0 69 0

UNSAT Performance Performance

Solver Error Score Correct Score CPU Time Score Wall Time Score Solved Solved UNSAT Unsolved Abstained Timeout Memout
cvc5 0 25595 308.21 368.31 485 485 8 0 8 0
SMTInterpol 0 22361 10619.46 9125.19 418 418 75 0 69 0

24 seconds Performance Performance

Solver Error Score Correct Score CPU Time Score Wall Time Score Solved Solved UNSAT Unsolved Abstained Timeout Memout
cvc5 0 25563 94.33 154.27 484 484 0 9 0 0
SMTInterpol 0 21343 1410.21 556.89 400 400 0 93 0 0