SMT-COMP 2025

The International Satisfiability Modulo Theories (SMT) Competition.

GitHub

SMT-COMP 2025

UFBVDTNIRA (Single Query Track)

Competition results for the UFBVDTNIRA logic in the Single Query Track. Chart

Results were generated on 2025-08-11

Benchmarks: 629
Time Limit: 1200 seconds
Memory Limit: 30720 GB

Winners

Sequential Performance Parallel Performance SAT Performance (parallel) UNSAT Performance (parallel) 24 seconds Performance (parallel)
cvc5 cvc5 - cvc5 cvc5

Sequential Performance Performance

Solver Error Score Correct Score CPU Time Score Wall Time Score Solved Solved SAT Solved UNSAT Unsolved Abstained Timeout Memout
cvc5 0 510 1417.90 1481.30 510 0 510 119 0 63 0
SMTInterpol 0 414 11176.28 9564.12 414 0 414 215 0 153 0

Parallel Performance Performance

Solver Error Score Correct Score CPU Time Score Wall Time Score Solved Solved SAT Solved UNSAT Unsolved Abstained Timeout Memout
cvc5 0 510 1417.90 1481.30 510 0 510 119 0 63 0
SMTInterpol 0 414 11176.28 9564.12 414 0 414 215 0 153 0

UNSAT Performance Performance

Solver Error Score Correct Score CPU Time Score Wall Time Score Solved Solved SAT Solved UNSAT Unsolved Abstained Timeout Memout
cvc5 0 510 1417.90 1481.30 510 0 510 6 113 6 0
SMTInterpol 0 414 11176.28 9564.12 414 0 414 102 113 86 0

24 seconds Performance Performance

Solver Error Score Correct Score CPU Time Score Wall Time Score Solved Solved SAT Solved UNSAT Unsolved Abstained Timeout Memout
cvc5 0 506 107.70 170.42 506 0 506 56 67 0 0
SMTInterpol 0 390 1310.67 517.77 390 0 390 13 226 0 0