The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the UFBVDT logic in the Single Query Track. Chart
Results were generated on 2025-08-11
Benchmarks: 1
Time Limit: 1200 seconds
Memory Limit: 30720 GB
Sequential Performance | Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
---|---|---|---|---|
- | - | - | - | - |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
---|---|---|---|---|---|---|---|---|---|---|---|
SMTInterpol | 0 | 0 | 0.00 | 0.00 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
cvc5 | 0 | 0 | 0.00 | 0.00 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
---|---|---|---|---|---|---|---|---|---|---|---|
SMTInterpol | 0 | 0 | 0.00 | 0.00 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
cvc5 | 0 | 0 | 0.00 | 0.00 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
---|---|---|---|---|---|---|---|---|---|---|---|
cvc5 | 0 | 0 | 0.00 | 0.00 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |