The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the QF_UFNRA logic in the Model Validation Track. Chart
Results were generated on 2025-08-11
Benchmarks: 31
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Sequential Performance | Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|---|
| cvc5 | cvc5 | cvc5 | - | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 29 | 3606.54 | 3610.58 | 29 | 29 | 2 | 0 | 2 | 0 |
| SMTInterpol | 0 | 2 | 0.86 | 0.86 | 2 | 2 | 29 | 0 | 0 | 0 |
| Yices2 | 4 | 26 | 217.35 | 220.63 | 26 | 26 | 5 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 29 | 3606.54 | 3610.58 | 29 | 29 | 2 | 0 | 2 | 0 |
| SMTInterpol | 0 | 2 | 0.86 | 0.86 | 2 | 2 | 29 | 0 | 0 | 0 |
| Yices2 | 4 | 26 | 217.35 | 220.63 | 26 | 26 | 5 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 29 | 3606.54 | 3610.58 | 29 | 29 | 2 | 0 | 2 | 0 |
| SMTInterpol | 0 | 2 | 0.86 | 0.86 | 2 | 2 | 29 | 0 | 0 | 0 |
| Yices2 | 4 | 26 | 217.35 | 220.63 | 26 | 26 | 5 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 12 | 54.23 | 55.68 | 12 | 12 | 0 | 19 | 0 | 0 |
| SMTInterpol | 0 | 2 | 0.86 | 0.86 | 2 | 2 | 27 | 2 | 0 | 0 |
| Yices2 | 4 | 24 | 22.35 | 25.36 | 24 | 24 | 5 | 2 | 0 | 0 |