The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the QF_UFLRA logic in the Incremental Track. Chart
Results were generated on 2025-08-11
Benchmarks: 1529
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|
| cvc5 | - | - | Yices2 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 13246 | 24988.75 | 24984.47 | 0 | 1529 | 0 | 6 | 0 |
| Yices2 | 0 | 13233 | 9757.95 | 9745.29 | 0 | 1529 | 0 | 4 | 0 |
| SMTInterpol | 0 | 12646 | 34820.51 | 32774.21 | 0 | 1529 | 0 | 26 | 0 |
| OpenSMT | 0 | 12208 | 51955.02 | 51954.48 | 0 | 1529 | 0 | 38 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| Yices2 | 0 | 12599 | 1064.32 | 1064.32 | 0 | 1481 | 48 | 0 | 0 |
| OpenSMT | 0 | 6787 | 1042.98 | 1042.98 | 0 | 1392 | 137 | 9 | 0 |
| cvc5 | 0 | 6744 | 2108.76 | 2108.76 | 0 | 1420 | 109 | 0 | 0 |
| SMTInterpol | 0 | 6482 | 2671.18 | 2671.18 | 0 | 1385 | 144 | 0 | 0 |