SMT-COMP 2025

The International Satisfiability Modulo Theories (SMT) Competition.

GitHub

SMT-COMP 2025

QF_UFIDL (Model Validation Track)

Competition results for the QF_UFIDL logic in the Model Validation Track. Chart

Results were generated on 2025-08-11

Benchmarks: 206
Time Limit: 1200 seconds
Memory Limit: 30720 GB

Winners

Sequential PerformanceParallel PerformanceSAT Performance (parallel)UNSAT Performance (parallel)24 seconds Performance (parallel)
OpenSMTOpenSMTOpenSMT-SMTInterpol

Sequential Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATUnsolvedAbstainedTimeoutMemout
OpenSMT02017873.147899.442012015050
SMTInterpol01819092.287717.80181181250250
cvc5017724902.5324928.37177177290290
Yices2014314617.5014637.50143143630630

Parallel Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATUnsolvedAbstainedTimeoutMemout
OpenSMT02017873.147899.442012015050
SMTInterpol01819092.287717.80181181250250
cvc5017724902.5324928.37177177290290
Yices2014314617.5014637.50143143630630

SAT Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATUnsolvedAbstainedTimeoutMemout
OpenSMT02017873.147899.442012015050
SMTInterpol01819092.287717.80181181250250
cvc5017724902.5324928.37177177290290
Yices2014314617.5014637.50143143630630

24 seconds Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATUnsolvedAbstainedTimeoutMemout
SMTInterpol01641430.07605.3216416404200
OpenSMT0162504.17524.4716216204400
Yices2010964.8878.4410910909700
cvc5010775.5488.7110710709900