The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the QF_UFDTLIRA logic in the Unsat Core Track. Chart
Results were generated on 2025-08-11
Benchmarks: 17
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Sequential Performance | Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|---|
| cvc5 | cvc5 | - | cvc5 | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 162 | 2.62 | 4.73 | 17 | 17 | 0 | 0 | 0 | 0 |
| SMTInterpol | 0 | 162 | 7.75 | 7.74 | 17 | 17 | 0 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 162 | 2.62 | 4.73 | 17 | 17 | 0 | 0 | 0 | 0 |
| SMTInterpol | 0 | 162 | 7.75 | 7.74 | 17 | 17 | 0 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 162 | 2.62 | 4.73 | 17 | 17 | 0 | 0 | 0 | 0 |
| SMTInterpol | 0 | 162 | 7.75 | 7.74 | 17 | 17 | 0 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 162 | 2.62 | 4.73 | 17 | 17 | 0 | 0 | 0 | 0 |
| SMTInterpol | 0 | 162 | 7.75 | 7.74 | 17 | 17 | 0 | 0 | 0 | 0 |