SMT-COMP 2025

The International Satisfiability Modulo Theories (SMT) Competition.

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SMT-COMP 2025

QF_UFDTLIRA (Model Validation Track)

Competition results for the QF_UFDTLIRA logic in the Model Validation Track. Chart

Results were generated on 2025-08-11

Benchmarks: 80
Time Limit: 1200 seconds
Memory Limit: 30720 GB

Winners

Sequential Performance Parallel Performance SAT Performance (parallel) UNSAT Performance (parallel) 24 seconds Performance (parallel)
cvc5 cvc5 cvc5 - cvc5

Sequential Performance Performance

Solver Error Score Correct Score CPU Time Score Wall Time Score Solved Solved SAT Unsolved Abstained Timeout Memout
cvc5 0 80 12.14 21.89 80 80 0 0 0 0
SMTInterpol 0 80 32.86 34.53 80 80 0 0 0 0

Parallel Performance Performance

Solver Error Score Correct Score CPU Time Score Wall Time Score Solved Solved SAT Unsolved Abstained Timeout Memout
cvc5 0 80 12.14 21.89 80 80 0 0 0 0
SMTInterpol 0 80 32.86 34.53 80 80 0 0 0 0

SAT Performance Performance

Solver Error Score Correct Score CPU Time Score Wall Time Score Solved Solved SAT Unsolved Abstained Timeout Memout
cvc5 0 80 12.14 21.89 80 80 0 0 0 0
SMTInterpol 0 80 32.86 34.53 80 80 0 0 0 0

24 seconds Performance Performance

Solver Error Score Correct Score CPU Time Score Wall Time Score Solved Solved SAT Unsolved Abstained Timeout Memout
cvc5 0 80 12.14 21.89 80 80 0 0 0 0
SMTInterpol 0 80 32.86 34.53 80 80 0 0 0 0