The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the QF_UFDTLIA logic in the Model Validation Track. Chart
Results were generated on 2025-08-11
Benchmarks: 32
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Sequential Performance | Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|---|
| SMTInterpol | SMTInterpol | SMTInterpol | - | SMTInterpol |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| SMTInterpol | 0 | 32 | 3383.61 | 2868.39 | 32 | 32 | 0 | 0 | 0 | 0 |
| cvc5 | 0 | 32 | 5340.12 | 5345.03 | 32 | 32 | 0 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| SMTInterpol | 0 | 32 | 3383.61 | 2868.39 | 32 | 32 | 0 | 0 | 0 | 0 |
| cvc5 | 0 | 32 | 5340.12 | 5345.03 | 32 | 32 | 0 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| SMTInterpol | 0 | 32 | 3383.61 | 2868.39 | 32 | 32 | 0 | 0 | 0 | 0 |
| cvc5 | 0 | 32 | 5340.12 | 5345.03 | 32 | 32 | 0 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| SMTInterpol | 0 | 18 | 349.58 | 154.00 | 18 | 18 | 0 | 14 | 0 | 0 |
| cvc5 | 0 | 16 | 167.04 | 168.99 | 16 | 16 | 0 | 16 | 0 | 0 |