The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the QF_UFBVLIA logic in the Incremental Track. Chart
Results were generated on 2025-08-11
Benchmarks: 179
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|
| Yices2 | - | - | Yices2 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| Yices2 | 0 | 207 | 10.32 | 10.32 | 0 | 179 | 0 | 0 | 0 |
| cvc5 | 0 | 207 | 31.81 | 31.81 | 0 | 179 | 0 | 0 | 0 |
| SMTInterpol | 0 | 207 | 195.07 | 195.07 | 0 | 179 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| Yices2 | 0 | 207 | 10.32 | 10.32 | 0 | 179 | 0 | 0 | 0 |
| cvc5 | 0 | 207 | 31.81 | 31.81 | 0 | 179 | 0 | 0 | 0 |
| SMTInterpol | 0 | 206 | 170.08 | 170.08 | 0 | 178 | 1 | 0 | 0 |