The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the QF_UFBVDT logic in the Model Validation Track. Chart
Results were generated on 2025-08-11
Benchmarks: 10
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Sequential Performance | Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|---|
| cvc5 | cvc5 | cvc5 | - | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 10 | 141.16 | 142.42 | 10 | 10 | 0 | 0 | 0 | 0 |
| SMTInterpol | 0 | 7 | 1575.59 | 1446.46 | 7 | 7 | 3 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 10 | 141.16 | 142.42 | 10 | 10 | 0 | 0 | 0 | 0 |
| SMTInterpol | 0 | 7 | 1575.59 | 1446.46 | 7 | 7 | 3 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 10 | 141.16 | 142.42 | 10 | 10 | 0 | 0 | 0 | 0 |
| SMTInterpol | 0 | 7 | 1575.59 | 1446.46 | 7 | 7 | 3 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 8 | 67.59 | 68.58 | 8 | 8 | 0 | 2 | 0 | 0 |
| SMTInterpol | 0 | 2 | 8.92 | 3.35 | 2 | 2 | 0 | 8 | 0 | 0 |