SMT-COMP 2025

The International Satisfiability Modulo Theories (SMT) Competition.

GitHub

SMT-COMP 2025

QF_RDL (Model Validation Track)

Competition results for the QF_RDL logic in the Model Validation Track. Chart

Results were generated on 2025-08-11

Benchmarks: 109
Time Limit: 1200 seconds
Memory Limit: 30720 GB

Winners

Sequential PerformanceParallel PerformanceSAT Performance (parallel)UNSAT Performance (parallel)24 seconds Performance (parallel)
Yices2Yices2Yices2-Yices2

Sequential Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATUnsolvedAbstainedTimeoutMemout
Yices20109593.97607.421091090000
OpenSMT01078468.738482.971071072020
cvc501051128.111140.951051054040
SMTInterpol01034438.333574.031031036060

Parallel Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATUnsolvedAbstainedTimeoutMemout
Yices20109593.97607.421091090000
OpenSMT01078468.738482.971071072020
cvc501051128.111140.951051054040
SMTInterpol01034438.333574.031031036060

SAT Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATUnsolvedAbstainedTimeoutMemout
Yices20109593.97607.421091090000
OpenSMT01078468.738482.971071072020
cvc501051128.111140.951051054040
SMTInterpol01034438.333574.031031036060

24 seconds Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATUnsolvedAbstainedTimeoutMemout
Yices2010388.53101.131031030600
cvc5097348.59360.34979701200
OpenSMT085189.60200.04858502400
SMTInterpol080807.75383.56808002900