SMT-COMP 2025

The International Satisfiability Modulo Theories (SMT) Competition.

GitHub

SMT-COMP 2025

QF_NonLinearRealArith (Model Validation Track)

Competition results for the QF_NonLinearRealArith division in the Model Validation Track. Chart

Results were generated on 2025-08-11

Benchmarks: 2777
Time Limit: 1200 seconds
Memory Limit: 30720 GB

Logics:

Winners

Sequential PerformanceParallel PerformanceSAT Performance (parallel)UNSAT Performance (parallel)24 seconds Performance (parallel)
SMT-RATSMT-RATSMT-RAT-SMT-RAT

Sequential Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATUnsolvedAbstainedTimeoutMemout
SMT-RAT0209022988.5723250.712090209068701610
cvc50201710890.6811139.672017201776001880
SMTInterpol0131893.891712.8013132764000
Yices243521057970.618234.822105210567201030

Parallel Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATUnsolvedAbstainedTimeoutMemout
SMT-RAT0209022988.5723250.712090209068701610
cvc50201710890.6811139.672017201776001880
SMTInterpol0131893.891712.8013132764000
Yices243521057970.618234.822105210567201030

SAT Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATUnsolvedAbstainedTimeoutMemout
SMT-RAT0209022988.5723250.712090209068701610
cvc50201710890.6811139.672017201776001880
SMTInterpol0131893.891712.8013132764000
Yices243521057970.618234.822105210567201030

24 seconds Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATUnsolvedAbstainedTimeoutMemout
SMT-RAT02024628.55879.062024202452023300
cvc502000525.22770.782000200055022700
SMTInterpol0738.2517.377727591100
Yices24312075646.72905.882075207556114100