SMT-COMP 2025

The International Satisfiability Modulo Theories (SMT) Competition.

GitHub

SMT-COMP 2025

QF_LIA (Model Validation Track)

Competition results for the QF_LIA logic in the Model Validation Track. Chart

Results were generated on 2025-08-11

Benchmarks: 4158
Time Limit: 1200 seconds
Memory Limit: 30720 GB

Winners

Sequential PerformanceParallel PerformanceSAT Performance (parallel)UNSAT Performance (parallel)24 seconds Performance (parallel)
OpenSMTOpenSMTOpenSMT-Yices2

Sequential Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATUnsolvedAbstainedTimeoutMemout
OpenSMT03975197961.09198484.773975397518301830
Yices20387044188.3144669.803870387028802880
SMTInterpol03715118582.3197797.953717371744104370
cvc503220121367.70121779.753220322093809380

Parallel Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATUnsolvedAbstainedTimeoutMemout
OpenSMT03975197961.09198484.773975397518301830
Yices20387044188.3144669.803870387028802880
SMTInterpol03717121099.5999881.173717371744104370
cvc503220121367.70121779.753220322093809380

SAT Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATUnsolvedAbstainedTimeoutMemout
OpenSMT03975197961.09198484.773975397518301830
Yices20387044188.3144669.803870387028802880
SMTInterpol03717121099.5999881.173717371744104370
cvc503220121367.70121779.753220322093809380

24 seconds Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATUnsolvedAbstainedTimeoutMemout
Yices2037082488.022944.3237083708045000
OpenSMT032104131.544527.0332103210094800
SMTInterpol0312612618.866188.19312631260103200
cvc5029312633.732990.75293129310122700