SMT-COMP 2025

The International Satisfiability Modulo Theories (SMT) Competition.

GitHub

SMT-COMP 2025

QF_IDL (Model Validation Track)

Competition results for the QF_IDL logic in the Model Validation Track. Chart

Results were generated on 2025-08-11

Benchmarks: 736
Time Limit: 1200 seconds
Memory Limit: 30720 GB

Winners

Sequential PerformanceParallel PerformanceSAT Performance (parallel)UNSAT Performance (parallel)24 seconds Performance (parallel)
Yices2Yices2Yices2-Yices2

Sequential Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATUnsolvedAbstainedTimeoutMemout
Yices2066318100.1818183.75663663730720
OpenSMT060840013.7040094.3060860812801280
cvc5059449413.1249493.0359459414201384
SMTInterpol038026144.5622160.3838038035602080

Parallel Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATUnsolvedAbstainedTimeoutMemout
Yices2066318100.1818183.75663663730720
OpenSMT060840013.7040094.3060860812801280
cvc5059449413.1249493.0359459414201384
SMTInterpol038026144.5622160.3838038035602080

SAT Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATUnsolvedAbstainedTimeoutMemout
Yices2066318100.1818183.75663663730720
OpenSMT060840013.7040094.3060860812801280
cvc5059449413.1249493.0359459414201384
SMTInterpol038026144.5622160.3838038035602080

24 seconds Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATUnsolvedAbstainedTimeoutMemout
Yices20599936.641009.93599599113600
OpenSMT04111373.161423.91411411032500
cvc503881253.531301.08388388034800
SMTInterpol02722750.851300.9227227212034400