The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the QF_DT logic in the Model Validation Track. Chart
Results were generated on 2025-08-11
Benchmarks: 1840
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Sequential Performance | Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|---|
| SMTInterpol | SMTInterpol | SMTInterpol | - | SMTInterpol |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| SMTInterpol | 0 | 1806 | 2901.93 | 2770.61 | 1806 | 1806 | 34 | 0 | 32 | 0 |
| cvc5 | 0 | 1229 | 5055.51 | 5206.08 | 1229 | 1229 | 611 | 0 | 8 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| SMTInterpol | 0 | 1806 | 2901.93 | 2770.61 | 1806 | 1806 | 34 | 0 | 32 | 0 |
| cvc5 | 0 | 1229 | 5055.51 | 5206.08 | 1229 | 1229 | 611 | 0 | 8 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| SMTInterpol | 0 | 1806 | 2901.93 | 2770.61 | 1806 | 1806 | 34 | 0 | 32 | 0 |
| cvc5 | 0 | 1229 | 5055.51 | 5206.08 | 1229 | 1229 | 611 | 0 | 8 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| SMTInterpol | 0 | 1798 | 856.50 | 847.61 | 1798 | 1798 | 2 | 40 | 0 | 0 |
| cvc5 | 0 | 1200 | 229.79 | 375.96 | 1200 | 1200 | 603 | 37 | 0 | 0 |