SMT-COMP 2025

The International Satisfiability Modulo Theories (SMT) Competition.

GitHub

SMT-COMP 2025

QF_Bitvec (Model Validation Track)

Competition results for the QF_Bitvec division in the Model Validation Track. Chart

Results were generated on 2025-08-11

Benchmarks: 8211
Time Limit: 1200 seconds
Memory Limit: 30720 GB

Logics:

Winners

Sequential PerformanceParallel PerformanceSAT Performance (parallel)UNSAT Performance (parallel)24 seconds Performance (parallel)
BitwuzlaBitwuzlaBitwuzla-Bitwuzla

Sequential Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATUnsolvedAbstainedTimeoutMemout
Bitwuzla0816638291.1939296.7181668166450394
Yices20812173011.2174029.3681218121900890
cvc508049118478.39119484.1980498049162014912
SMTInterpol03878192678.88166115.10388738874324035250

Parallel Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATUnsolvedAbstainedTimeoutMemout
Bitwuzla0816638291.1939296.7181668166450394
Yices20812173011.2174029.3681218121900890
cvc508049118478.39119484.1980498049162014912
SMTInterpol03887203622.49176633.66388738874324035250

SAT Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATUnsolvedAbstainedTimeoutMemout
Bitwuzla0816638291.1939296.7181668166450394
Yices20812173011.2174029.3681218121900890
cvc508049118478.39119484.1980498049162014912
SMTInterpol03887203622.49176633.66388738874324035250

24 seconds Performance Performance

SolverError ScoreCorrect ScoreCPU Time ScoreWall Time ScoreSolvedSolved SATUnsolvedAbstainedTimeoutMemout
Bitwuzla079948678.449656.8479947994021700
Yices2077386171.977132.8277387738047300
cvc50727114982.4115875.2572717271094000
SMTInterpol0316419399.809266.4631643164321472600