The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the QF_AUFLIA logic in the Model Validation Track. Chart
Results were generated on 2025-08-11
Benchmarks: 300
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Sequential Performance | Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|---|
| cvc5 | cvc5 | cvc5 | - | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 300 | 155.49 | 191.69 | 300 | 300 | 0 | 0 | 0 | 0 |
| SMTInterpol | 0 | 300 | 341.64 | 199.63 | 300 | 300 | 0 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 300 | 155.49 | 191.69 | 300 | 300 | 0 | 0 | 0 | 0 |
| SMTInterpol | 0 | 300 | 341.64 | 199.63 | 300 | 300 | 0 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 300 | 155.49 | 191.69 | 300 | 300 | 0 | 0 | 0 | 0 |
| SMTInterpol | 0 | 300 | 341.64 | 199.63 | 300 | 300 | 0 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 300 | 155.49 | 191.69 | 300 | 300 | 0 | 0 | 0 | 0 |
| SMTInterpol | 0 | 300 | 341.64 | 199.63 | 300 | 300 | 0 | 0 | 0 | 0 |