The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the LRA logic in the Incremental Track. Chart
Results were generated on 2025-08-11
Benchmarks: 5
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|
| cvc5 | - | - | SMTInterpol |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 15969 | 66.51 | 66.51 | 0 | 5 | 0 | 0 | 0 |
| UltimateEliminator+MathSAT | 0 | 15969 | 92.77 | 92.77 | 0 | 5 | 0 | 0 | 0 |
| SMTInterpol | 0 | 12736 | 1220.55 | 1220.55 | 0 | 5 | 0 | 1 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| SMTInterpol | 0 | 12014 | 21.45 | 21.45 | 0 | 4 | 1 | 0 | 0 |
| cvc5 | 0 | 7443 | 11.46 | 11.46 | 0 | 4 | 1 | 0 | 0 |
| UltimateEliminator+MathSAT | 0 | 7443 | 47.00 | 47.00 | 0 | 4 | 1 | 0 | 0 |