The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the LIA logic in the Incremental Track. Chart
Results were generated on 2025-08-11
Benchmarks: 6
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|
| cvc5 | - | - | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 25393 | 17.07 | 17.07 | 0 | 6 | 0 | 0 | 0 |
| SMTInterpol | 0 | 25393 | 24.95 | 24.95 | 0 | 6 | 0 | 0 | 0 |
| UltimateEliminator+MathSAT | 0 | 13859 | 64.33 | 64.33 | 0 | 6 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 25393 | 17.07 | 17.07 | 0 | 6 | 0 | 0 | 0 |
| SMTInterpol | 0 | 25393 | 24.95 | 24.95 | 0 | 6 | 0 | 0 | 0 |
| UltimateEliminator+MathSAT | 0 | 13859 | 64.33 | 64.33 | 0 | 6 | 0 | 0 | 0 |