The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the BV logic in the Incremental Track. Chart
Results were generated on 2025-08-11
Benchmarks: 18
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|
| cvc5 | - | - | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 35835 | 2156.58 | 2156.58 | 0 | 18 | 0 | 7 | 0 |
| Bitwuzla | 0 | 35062 | 505.43 | 505.43 | 0 | 18 | 0 | 6 | 0 |
| SMTInterpol | 0 | 20489 | 2226.08 | 2226.08 | 0 | 18 | 0 | 6 | 0 |
| UltimateEliminator+MathSAT | 0 | 18912 | 170.17 | 170.17 | 0 | 18 | 0 | 1 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 25129 | 91.71 | 91.71 | 0 | 10 | 8 | 4 | 0 |
| Bitwuzla | 0 | 21121 | 55.56 | 55.56 | 0 | 12 | 6 | 6 | 0 |
| UltimateEliminator+MathSAT | 0 | 13770 | 96.92 | 96.92 | 0 | 16 | 2 | 0 | 0 |
| SMTInterpol | 0 | 13642 | 72.71 | 72.71 | 0 | 14 | 4 | 3 | 0 |