The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the AUFNIRA logic in the Incremental Track. Chart
Results were generated on 2025-08-11
Benchmarks: 165
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|
| cvc5 | - | - | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 3049 | 28073.56 | 28090.46 | 0 | 165 | 0 | 26 | 0 |
| SMTInterpol | 0 | 1891 | 101988.29 | 68061.50 | 0 | 165 | 0 | 42 | 0 |
| UltimateEliminator+MathSAT | 0 | 0 | 597.62 | 338.71 | 0 | 165 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 3012 | 52.53 | 52.53 | 0 | 138 | 27 | 3 | 0 |
| SMTInterpol | 0 | 1426 | 122.74 | 122.74 | 0 | 83 | 82 | 0 | 0 |
| UltimateEliminator+MathSAT | 0 | 0 | 597.62 | 338.71 | 0 | 165 | 0 | 0 | 0 |