The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the AUFBVDTLIA logic in the Unsat Core Track. Chart
Results were generated on 2025-08-11
Benchmarks: 139
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Sequential Performance | Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|---|
| SMTInterpol | SMTInterpol | - | SMTInterpol | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| SMTInterpol | 0 | 83 | 2458.34 | 1924.14 | 133 | 133 | 6 | 0 | 5 | 0 |
| cvc5 | 0 | 82 | 33.11 | 50.47 | 139 | 139 | 0 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| SMTInterpol | 0 | 83 | 2458.34 | 1924.14 | 133 | 133 | 6 | 0 | 5 | 0 |
| cvc5 | 0 | 82 | 33.11 | 50.47 | 139 | 139 | 0 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| SMTInterpol | 0 | 83 | 2458.34 | 1924.14 | 133 | 133 | 6 | 0 | 5 | 0 |
| cvc5 | 0 | 82 | 33.11 | 50.47 | 139 | 139 | 0 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 82 | 33.11 | 50.47 | 139 | 139 | 0 | 0 | 0 | 0 |
| SMTInterpol | 0 | 81 | 468.29 | 202.05 | 124 | 124 | 0 | 15 | 0 | 0 |