The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the UFDTNIA logic in the Incremental Track.
Page generated on 2023-07-06 16:05:24 +0000
Benchmarks: 139 Time Limit: 1200 seconds Memory Limit: 60 GB
Parallel Performance |
---|
cvc5 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5 | 0 | 384 | 1132.87 | 1148.3 | 362 | 56 | 0 |
SMTInterpol | 0 | 0 | 0.0 | 0.0 | 746 | 0 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.