The International Satisfiability Modulo Theories (SMT) Competition.
Home
Introduction
Benchmark Submission
Publications
SMT-LIB
Previous Editions
Competition results for the UFDTLIRA logic in the Unsat Core Track.
Page generated on 2023-07-06 16:05:43 +0000
Benchmarks: 2873 Time Limit: 1200 seconds Memory Limit: 60 GB
| Sequential Performance | Parallel Performance |
|---|---|
| cvc5 | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
|---|---|---|---|---|---|---|
| 2021-cvc5-ucn | 0 | 76127 | 172.115 | 171.132 | 3 | 0 |
| cvc5 | 0 | 73379 | 166.3 | 165.245 | 7 | 0 |
| SMTInterpol | 0 | 73090 | 12522.547 | 7956.011 | 80 | 0 |
| Vampire | 0 | 6686 | 31.679 | 30.239 | 52 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
|---|---|---|---|---|---|---|
| 2021-cvc5-ucn | 0 | 76127 | 172.115 | 171.132 | 3 | 0 |
| cvc5 | 0 | 73379 | 166.3 | 165.245 | 7 | 0 |
| SMTInterpol | 0 | 73090 | 12522.547 | 7956.011 | 79 | 0 |
| Vampire | 0 | 6686 | 31.679 | 30.239 | 38 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.