The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the UFDTLIA logic in the Unsat Core Track.
Page generated on 2023-07-06 16:05:43 +0000
Benchmarks: 202 Time Limit: 1200 seconds Memory Limit: 60 GB
Sequential Performance | Parallel Performance |
---|---|
Vampire | Vampire |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
Vampire | 0 | 1606 | 3551.999 | 907.609 | 74 | 0 |
2021-cvc5-ucn | 0 | 444 | 1963.064 | 1963.333 | 172 | 0 |
cvc5 | 0 | 441 | 1944.399 | 1944.876 | 171 | 0 |
SMTInterpol | 0 | 153 | 2874.475 | 2497.243 | 182 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
Vampire | 0 | 1606 | 3551.999 | 907.609 | 72 | 0 |
2021-cvc5-ucn | 0 | 444 | 1963.064 | 1963.333 | 172 | 0 |
cvc5 | 0 | 441 | 1944.399 | 1944.876 | 171 | 0 |
SMTInterpol | 0 | 153 | 2874.475 | 2497.243 | 182 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.