SMT-COMP

The International Satisfiability Modulo Theories (SMT) Competition.

GitHub

Home
Introduction
Benchmark Submission
Publications
SMT-LIB
Previous Editions

SMT-COMP 2023

Rules
Benchmarks
Specs
Model Validation Track
Proof Exhibition Track
Parallel & Cloud Tracks
Participants
Results
Statistics
Comparisons
Slides

QF_UFLRA (Proof Exhibition Track)

Competition results for the QF_UFLRA logic in the Proof Exhibition Track.

Page generated on 2023-07-06 16:06:18 +0000

Benchmarks: 150
Time Limit: 1200 seconds
Memory Limit: 60 GB

This track is experimental. Solvers are only ranked by performance, but no winner is selected.

Sequential Performance

Solver Error Score Correct Score CPU Time Score Wall Time ScoreUnsolvedTimeout Memout
SMTInterpol 0 148 1468.401 622.35422 0
cvc5-lfsc 0 146 555.056 553.50644 0
cvc5 0 10 257.206 254.932140139 0

Parallel Performance

Solver Error Score Correct ScoreCPU Time ScoreWall Time ScoreUnsolvedTimeout Memout
SMTInterpol 0 1481468.401622.35422 0
cvc5-lfsc 0 146555.056553.50644 0
cvc5 0 10257.206254.932140139 0

n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.